Accellera Day India 2018
November 14, 2018
9:00am – 5:00pm
Radisson Blu Bengaluru
90-4 Marathahalli, Outer Ring Road
Special Guest speaker Cliff Cummings, Portable Stimulus, and more!
Accellera Day India will be an in-depth full day technical program held in Bangalore, India on November 14, 2018. The format will be similar to Accellera Day held each year at DVCon U.S.
A tutorial exploring the new Portable Test and Stimulus Standard 1.0 will be held in the morning with presenters Sharon Rosenberg, Senior Architect for Cadence and Pradeep Salla, Functional Verification Technical Manager for Mentor, A Siemens Business. The in-depth technical tutorial will focus on a set of typical design use cases from a variety of applications and will show how to use the new standard to create an abstract model of verification intent. The tutorial will then demonstrate how these models can be used to generate scenarios to be executed on the different platforms and environments used in a development process, and how the models can be reused and leveraged from project to project.
A luncheon and keynote given by Qualcomm’s Srini Maddali will follow the morning tutorial. Maddali is Vice President of Technology at Qualcomm India and is responsible for Qualcomm’s cellular modem development.
In the afternoon, SystemVerilog and UVM guru Cliff Cummings will dive into the changes and features that are part of the new IEEE 1800.2 standard for UVM. Attendees will benefit from his favorite UVM tips and tricks, and he’ll offer clarification and guidelines for UVM messaging and verbosities. Cummings will also explain the origins of the two different techniques to define UVM transactions and execute sequences, including the advantages and disadvantages of each. With this knowledge, attendees will have a greater understanding of all publicly available UVM examples. Cummings is President of Sunburst Design, specializing in SystemVerilog, Synthesis and UVM Verification training. He’s presented hundreds of seminars and training classes, has been an active participant on every IEEE Verilog and SystemVerilog committee and has presented more than 50 papers, including 20 that were voted “Best Paper.”
|Start Time||End Time||Description|
|9:00am||9:15am||Welcome & Overview - General Chair|
|9:15am||10:30am||Portable Stimulus part 1|
|11:00am||12:15pm||Portable Stimulus part 2|
|12:45pm||1:30pm||Keynote - Srini Maddali of Qualcomm|
|1:30pm||3:00pm||UVM part 1|
|3:15pm||4:45pm||UVM part 2|
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Become a Sponsor
|Sponsorship||Cost INR||Number Avail.|
* Sponsor supplies materials
- Sanjay Muchini, Qualcomm (Lead)
- Pradeep Salla, Mentor
- Veeresh Shetty, Mentor
- Subramanian Karthikeyan, Qualcomm
- Abhijeet Khopkar, Synopsys
- Ashok Natarajan, Intel
- Lokesh P, Cadence
- Aparna Dey, Cadence
- Lu Dai, Qualcomm
- Lynn Garibaldi, Accellera