Video Presentations and Tutorials

Technical Tutorial: "IEEE-Compatible UVM Reference Implementation and Verification Components"

UVM 2/26/18

This tutorial introduces you to the new reference implementation aligned with IEEE 1800.2 and created by the Accellera UVM Working Group. It helps you gain the practical knowledge you need to adopt the IEEE 1800.2™ Standard for UVM.

Presented by Justin Refice, NVIDIA; Mark Strickland, Cisco; Uwe Simm, Cadence; Mark Peryer, Mentor, A Siemens Business; Srivatsa Vasudevan, Synopsys

Topics:

Introduction, New Users and Migrators from Pre-1.2
Objects and Policies
Abstract Factory, Deferred Initialization and Dynamic UVM_Reg Mapping
Configuration, Callbacks and Reporting

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Technical Tutorial: "Portable Test and Stimulus: The Next Level of Verification Productivity is Here"

2/26/18

Presented by Tom Fitzpatrick, Mentor, a Siemens Business; Adnan Hamid, Breker

Panel: Faris Khundakjie, Intel; Adnan Hamid, Breker; Sharon Rosenberg, Cadence; Tom Fitzpatrick, Mentor, a Siemens Business; Srivatsa Vasudevan, Synopsys; Karthick Gururaj, Vayavya

Topics:

Use the Portable Test and Stimulus Standard to create an abstract model of your verification intent
Generate scenarios from these models to be executed on the different platforms and environments used in your development process
Reuse and leverage these models from project to project
Panel discussion and Q&A with members of the Accellera Portable Stimulus Working Group

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Technical Tutorial: "Introducing IEEE 1800.2 – The Next Step for UVM"

UVM 2/27/17

Presented by Thomas Alsop, Intel; Srivatsa Vasudevan, Synopsys; Mark Glasser, NVIDIA; Srinivasan Venkataramanan, VerifWorks; Krishna Thottempudi, Qualcomm

Topics:

Introduction to UVM
Changes from Accellera UVM, Additions & Clarifications
TLM and Register Update for IEEE 1800.2
UVM for RTL Designers

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Technical Tutorial: "SystemC Design and Verification – Solidifying the Abstraction Above RTL"

SystemC 2/27/17

Presented by Peter Frey, Mentor; Trever Wieman, Intel; Mike Meredith, Cadence

Topics:

Synthesizable Subset Update
SystemC Configuration Tutorial — A Preview of the Draft Standard
UVM-SystemC Standardization Status and Latest Developments

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Technical Tutorial: "Creating Portable Stimulus Models with the Upcoming Accellera Standard"

2/27/17

Presented by Faris Khundakjie, Intel; Tom Fitzpatrick, Mentor; Sharon Rosenberg, Cadence; Adnan Hamid, Breker; Srivatsa Vasudevan, Synopsys; Sandeep Pendharkar, Vayavya

This tutorial presents an introduction to the Portable Stimulus standard’s main features leveraging a series of usage examples defined by PSWG members that represent many of the common challenges faced in today’s multi-core designs.

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Technical Tutorial: "SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling"

2/29/16

Presented by Martin Vlach, Mentor Graphics; Scott Little, Intel

This tutorial provides an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard. The tutorial covers requirements and areas of concern for the new standard, data types, the new nodetype, connectivity, hierarchy, adapters, power-aware, filtering, and other concepts.

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Technical Tutorial: "SVA Advanced Topics: SVAUnit and Assertions for Formal"

2/29/16

Presented by Ionut Ciocirîan, AMIQ; Andra Radu, AMIQ; Rodrigo Calderón-Rico, Intel; Israel Tapia, Intel

Topics:

SystemVerilog Assertions Verification with SVAUnit
Formal Specification, SystemVerilog Assertions & Coverage

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Technical Tutorial: "Cut Your Design Time in Half with Higher Abstraction"

SystemC 2/29/16

Presented by Bob Condon, Intel; Frederic Doucet, Qualcomm; Peter Frey, Mentor Graphics; Mike Meredith, Cadence; Dirk Seynhaeve, Intel

Topics:

How High-level Synthesis Works: An Intro for Hardware Designers
The Proposed Accellera SystemC Synthesizable Subset
High-Level Synthesis and Verification
HLS in the Wild — Intel's Experience
HLS for the FPGA/Programmable Market
SystemC Synthesis Standard: Which Topics for Next Round?

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Technical Tutorial: "UVM Tips and Tricks Plus Preparing for IEEE UVM"

UVM 2/29/16

Presented by: Doug Perry, Doulos; Srivatsa Vasudevan, Synopsys. Slides by Srinivasan Venkataramanan, VerifWorks

Topics:

UVM Compile Time Tips and Tricks
UVM Runtime Tips and Tricks
Accellera Standards Update - UVM and IEEE-1800.2

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Accellera Standards Technical Update

11/11/15

Presented by: Uwe Simm, Cadence Design Systems; Sharon Rosenberg, Cadence Design Systems; Erwin de Kock, NXP Semiconductors; Philipp A. Hartmann, Intel

Experts in the Accellera standardization give a technical update on the recent standardization activities in the various working groups: Universal Verification Methodology, Portable Stimulus, IP-XACT, and SystemC.

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System-Level Modeling for Today and Tomorrow with SystemC

11/11/15

Presented by: Philipp A Hartmann, Intel; Martin Barnasconi, NXP; Stephan Schulz, Fraunhofer

Topics:

SystemC Standards Update
What is Needed Beyond SystemC and TLM-2.0 for Bigger Systems?

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Technical Tutorial: "SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set"

3/2/15

Presented by Stuart Sutherland, Sutherland HDL; Junette Tan, PMC; Mike Schaffstein, Qualcomm

Topics:

Ways Design Engineers Can Benefit from the Use of SystemVerilog Assertions
Experience from Four Years of SVD Adoption
No Excuses for Not Using SystemVerilog in Your Next Design
Panel Discussion

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Technical Tutorial: "Automating Design and Verification of Embedded Systems Using Metamodeling and Code Generation Techniques"

3/2/15

Presented by Wolfgang Ecker, Infineon; Michael Velten, Infineon; Rainer Findenig, Intel; Daniel Müller-Gritscheneder, Technical University of Munich; Wolfgang Mueller, University of Paderborn

Topics:

What Is Metamodeling and Code Generation All About
Well Known Metamodels in EDA and Design: UML/SysML
Well Known Metamodels in EDA and Design: IP-XACT
Tutorial: VHDL Code Generation from IP-XACT Using the Eclipse Modeling Framework (EMF)

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Technical Tutorial: "Next Generation Design and Verification Today"

3/2/15

Presented by Mike Bartley, TVS; Kyle Newman, Texas Instruments; Erich Marschner, Vice-Chair, IEEE P1801 WG

Topics:

Requirements-driven Verification Methodology (for Standards Compliance)
Using UCIS to Combine Verification Data from Multiple Tools
UVM REG: Path Towards Coverage Automation in AMS Simulations
New Developments in UPF 3.0

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Technical Tutorial: "SystemC Standardization Update Including UVM for SystemC"

SystemC 3/2/15

Presented by Andy Goodrich, Cadence

Topics:

Accellera Systems Initiative SystemC Standards Update
Introduction to the Universal Verification Methodology in SystemC

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Technical Tutorial: "Using UPF for Low Power Design and Verification"

UPF 3/3/14

Presented by Erich Marschner, Mentor Graphics; John Biggs, ARM; Sushma Honnavara-Prasad, Broadcom; David Cheng, Cadence; Shreedhar Ramachandra, Synopsys

Topics include:

Low Power Design and Verification Challenges
Introduction to UPF
UPF Basic Concepts and Terminology
UPF Semantics and Usage
Hard IP Modeling with Liberty and Verilog
Power Model and Power Management Cell Commands
Low Power Design Methodology for IP Providers
SoC-Level Design and Verification

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Technical Tutorial: "Case Studies in SystemC"

SystemC 3/3/14

Presented by John Aynsley, Doulos; Henrik Svensson, Ericsson; Christian Sauer, Cadence; Martin Barnasconi, NXP Semiconductors; Donald Cramb, Synopsys; John Stickley, Mentor Graphics; Gordon Allen, Mentor Graphics

Topics include:

Hints and Tips for Exploiting the Latest Features of SystemC
TLM Use Cases at Ericsson AB
Efficient Abstractions for AMS System-level Design
UVM for SystemC Users

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Technical Tutorial: "OCP: The Journey Continues"

OCP 3/3/14

Presented by Drew Wingard, Sonics; Steve McMaster, Synopsys; Herve Alexanian, Sonics; Prashant Karandikar, Texas Instruments

Topics:

Introduction to OCP
Verification Support for OCP
SystemC TLM 2.0 Support for OCP
IP-XACT Support for OCP
OCP Futures

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Technical Tutorial: "Experience the Next ~Wave~ of Analog and Digital Signal Processing using SystemC AMS 2.0"

SystemC 3/3/14

Presented by Martin Barnasconi, NXP Semiconductors; Karsten Einwich, Fraunhofer IIS; François Pêcheux, Université Pierre et Marie Curie; Torsten Mähne, Université Pierre et Marie Curie

Topics:

Tutorial Introduction
SystemC AMS Introduction
Lab: Sine Source Connected to a Sink
Models of Computation
Lab: Filtering and A/D Conversion
SystemC AMS 2.0 and Applications
Lab: Vibration Sensor
Workshop Summary

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Technical Tutorial: "UVM — What's Now and What's Next"

UVM 3/3/14

Presented by Adam Sherer, Accellera; John Aynsley, Doulos; Shawn Honess, Synopsys; Tom Fitzpatrick, Mentor Graphics; Uwe Simm, Cadence

Topics:

UVM Working Group Update
UVM Overview and Library Concepts
Stimulus Generation
UVM Register Layer
UVM 1.2 Introduction

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Technical Tutorial: "Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™"

UPF 2/25/13

Presented by Erich Marschner, Mentor Graphics; Qi Wang, Cadence; John Biggs, ARM; Sushma Honnavarra-Prasad, Broadcom; Jeffrey Lee, Synopsys

Topics:

Introduction
Low Power Design and Verification
Unified Power Format (UPF)
Power Intent Specification Methodology
Using UPF for IP Design
Using UPF for System Design
What's New in UPF 2.1

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Technical Tutorial: "User Experiences at the Forefront of Mixed-Signal Design and Verification"

2/25/13

Presented by Helene Thibieroz, Synopsys; Henry Chang, Designer's Guide Consulting; Jonathan David, Qualcomm Atheros; Christophe Curis, STMicroelectronics; Ozan Erdogan, Maxim Integrated; Martin Barnasconi, NXP Semiconductors; Thilo Voertler, Fraunhofer Institute; Thang Nguyen, Infineon

Topics:

Common Mistakes Made in Analog Verification
The Mixed-Signal Verification Challenge
Mixed-Signal Validations for a BIST on ADC
SystemVerilog Modeling for Mixed-Signal SoC Verification
AMS System-Level Design and Verification for Automotive Applications
The VERDI Project -- Mixed-Signal Verification and Validation for SystemC/AMS
FPGA and AMS Test Chip Approach for Complex SoC Product Design and Verification

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Technical Tutorial: "Increasing Productivity with SystemC in Complex System Design and Verification"

SystemC 2/25/13

Presented by Trevor Wieman, CCI WG Chair, Intel; David Black, Doulos; Stuart Swan, Cadence; Shabtay Matalon, Mentor Graphics; Jon McDonald, Mentor Graphics; Nithya Ruff, Synopsys; Charu Khosla, Synopsys

Topics:

Configuration, Control & Inspection Working Group Update
A SystemC Technology Demonstrator using the Xilinx Zynq™-7000
A Unified Design Flow for SystemC Virtual Platforms and High-Level Synthesis
From Virtual Prototyping to RTL Verification
Virtual Prototyping: You don't need a PHD to model in System C and TLM

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Technical Tutorial: "Lessons from the Trenches: Migrating Legacy Verification Environments to UVM"

UVM 2/25/13

Presented by John Aynsley, Doulos; Hassan Shehab, Intel; Richard Tseng, Qualcomm; Asad Khan, Texas Instruments; Mark Litterick, Verilab; Charles Zhang, Paradigm Works; Wesley Queen, IBM; Ravi Ram, Altera

Topics:

Anecdotes from Hundreds of UVM Adopters
Migrating from OVM to UVM — A Case Study
A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
UVM to the Rescue — Path to Robust Verification
OVM-to-UVM Migration — or There and Back Again, a Consultant's Tale
IBM Recommendations for OVM-to-UVM Migration
FPGA Chip Verification Using UVM

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Technical Tutorial: "An Introduction to IEEE 1666-2011, the New SystemC Standard"

SystemC 2/27/12

Presented by John Aynsley, Doulos; David Black, Doulos; and Tor Jeremiassen, Texas Instruments

Topics:

SystemC Refresher
Process Control
Stepping and Pausing the Scheduler
sc_vector
TLM-2.0
SystemC and O/S Threads
Virtualization of SystemC Model I/O
Draft SystemC Configuration Standard

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Technical Tutorial: "Verification and Automation Improvement Using IP-XACT"

IP-XACT 2/27/12

Presented by John Swanson, Synopsys; Kamlesh Pathak, STMicroelectronics; David Murray, Duolog Technologies; and Sylvain Duvillard, Magillem Design Services

Technical presentations:

Part 1: Improving Verification Efficiency using IP-XACT
Part 2: User Presentation: Verification and Automation Improvement Using IP-XACT
Part 3: IP-XACT and UVM
Part 4: IP-XACT Extensions

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Technical Tutorial: "An Introduction to the Unified Coverage Interoperability Standard"

2/27/12

Presented by Dr. Richard Ho, D. E. Shaw Research; Dr. Ambar Sarkar, Paradigm Works, Inc.

Presented by co-chairs of the UCIS Technical Committee, this video tutorial provides an overview of UCIS and its API and how users plan to enhance their verification flows using it.

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Technical Tutorial: "UVM: Ready, Set, Deploy!"

UVM 2/27/12

Presented by Tom Fitzpatrick, Mentor Graphics; John Aynsley, Doulos; Kathleen Meade, Cadence Design Systems; Adiel Khan, Synopsys; Vanessa Cooper, Verilab; Stephen D'Onofrio, Paradigm Works; Peter J. D'Antonio, The MITRE Corp.; John Fowler, AMD; Justin Refice, AMD; and Mark Strickland, Cisco Systems

Technical presentations:

Part 1: Base Classes in UVM
Part 2: Communication and Sequences
Part 3: Customizing Your UVM Environment
Part 4: Register Modeling in UVM
User Experience 1: Getting Started with UVM
User Experience 2: Stacking Verification Components in UVM
User Experience 3: OVM to UVM Transition
User Experience 4: VC Building Blocks with UVM

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Software-driven Verification using TLM-2.0 Virtual Platforms Video Tutorial

SystemC 2/28/11

Presented by David Black, XtremeEDA Corporation; John Aynsley, Doulos; Bill Bunton, LSI Corporation; Volkan Esen, Infineon Technologies; and Trevor Wieman, Intel Corporation

Technical presentations:

How We Got Here
Software-driven Verification using TLM-2.0 Virtual Platforms
LSI Axxia™ VDP Verification Using SystemC TLM-2.0
Software-Driven Test Environment for TLM-IP Verification
TLM-2.0 Hybrid Virtual Platforms

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NASCUG 16 Presentations

SystemC 6/6/11

Technical presentations:

SystemC IP Generation from Graphics and Verification with a UVM SystemVerilog Testbench
Verification Closure of SystemC Designs with Functional Coverage
Standard Methodology for Configuration, Control & Inspection of Models
Software Verification, Analysis and Profiling on SystemC TLM-2.0 Virtual Platforms
TLM-2.0: Miracle Cure or Snake Oil?
OSCI and IEEE P1666 Update

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SystemC Day 2011

2/28/11

Keynote: "Navigating the SoC Era"
Jim Hogan, Vista Ventures LLC

SystemC Technical presentations:

The New IEEE 1666 SystemC Standard
Low-cost SystemC Acceleration on Multi-core GNU/Linux Platforms
TLM Methodology to Enable Architecture Exploration via Co-simulation of SystemC Models with Legacy C/C++ Models
A Common System Memory Model for SoC Software and Architecture Models using a SystemC/TLM-2.0 Interface
OSCI Update

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NASCUG 13 Video Presentations

SystemC 6/13/10

Technical presentations:

How to Create Adaptors Between Modeling Abstraction Levels
Virtual Development Platforms -- What and How Much to Model?
Modeling Communication Systems Using the SystemC AMS Building Block Library
New Features for Process Control in SystemC
Generating Workload Models from TLM-2.0 Based Virtual Platforms for Efficient Architecture Performance Analysis

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